1. Field of the Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to nonvolatile semiconductor memory devices having three-level memory cells, and methods of operating the nonvolatile semiconductor memory devices.
This application claims priority to Korean Patent Application No. 10-2006-9631 filed on Feb. 1, 2006, the subject matter of which is incorporated by reference in its entirety.
2. Description of Related Art
Nonvolatile semiconductor memory devices retain stored data even when disconnected from an external power source. Accordingly, these types of memory devices are an especially popular way of providing long term data storage in electronic devices where power is limited or may be cut off, such as portable electronic devices.
There are a wide variety of nonvolatile memory devices, including, for example, ferroelectric random access memories (FRAMs), nonvolatile random access memories (NRAMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs), to name but a few. However, one especially popular form of nonvolatile memory is flash memory. Flash memory is a type of EEPROM where each memory cell is formed of a single metal-oxide semiconductor (MOS) transistor.
FIG. 1 shows an example of a typical flash memory cell. Referring to FIG. 1, a flash memory cell MC comprises a source “S” and a drain “D” formed in a semiconductor substrate. A current path is formed between source S and drain D. Memory cell MC further comprises a gate oxide film GOX formed on the semiconductor substrate, a floating gate FG formed on gate oxide film GOX, a dielectric oxide DOX film formed on floating gate FG, and a control gate CG formed on dielectric oxide DOX.
Memory cell MC is programmed to store data by applying appropriate bias voltages to control gate CG, drain D and source S, and the semiconductor substrate so that electrons become trapped in floating gate FG. Electrons can become trapped in floating gate FG, for example, by flowing electrons across the current path between source S and drain D while applying a high voltage to a word line WL connected to control gate CG. The high voltage on word line WL causes electrons flowing between source S and drain D to travel across gate oxide film GOX and become trapped in floating gate FG. Various alternative techniques exist for trapping electrons in floating gate FG, including Fowler-Nordheim tunneling, channel-initiated secondary electron injection, and channel hot electron injection, for example.
Memory cell MC is erased by removing trapped electrons from floating gate FG. This can be accomplished, for example by generating an electrical potential between source S or drain D and control gate CG the trapped electrons leave floating gate FG.
Electrons trapped in floating gate FG of memory cell MC tend to elevate a threshold voltage of memory cell MC. Here, the threshold voltage is a voltage that must be applied to control gate CG in order for current to flow between source S and drain D. In general, the electrons trapped in floating gate FG tend to elevate the threshold voltage of memory cell MC because these electrons partially cancel out an electrical field generated by the voltage applied to control gate CG, and therefore, a higher voltage must be used to cause current to flow between source S and drain D.
Memory cell MC stores one of two data values. These two data values are represented by two threshold voltage distributions illustrated in FIG. 2. Based on the threshold voltage distributions illustrated in FIG. 2, if memory cell MC has a threshold voltage higher than a reference voltage VM, then it stores a data value “0”. Otherwise, if the threshold voltage of memory cell MC is lower than reference voltage VM, then it stores a data value “1”. Accordingly, memory cell MC can be read by applying reference voltage VM to word line WL and determining whether current flows between source S and drain D.
In order to increase the amount of data that can be stored within a small area of a flash memory device, researchers have developed flash memory devices capable of storing data in more than two states. This is typically accomplished by a memory cell exhibiting more than two distinct threshold voltage distributions. For example, FIG. 3 illustrates four threshold voltage distributions for a memory cell capable of storing data in one of four different states. In general, the term “n-level nonvolatile memory cell” will be used in this written description to refer to memory cells capable of storing data in “n” different states. Accordingly, terms such as 2-level nonvolatile memory cell and 4-level nonvolatile memory cell are used to describe memory cells capable of storing data with 2 or 4 states, respectively.
A 4-level memory cell has twice the storage capacity of a 2-level memory cell. However, the margins between adjacent threshold voltage distributions in the 4-level memory cells are typically very small, for example, about 0.67V. Accordingly, 4-level memory cells tend to be more susceptible to errors than 2-level memory cells due to shifts in the threshold voltage distributions. These shifts can be caused, for example, by leakage currents.
Because the 4-level memory cells are more error prone than 2-level memory cells, the benefit of the additional storage capacity of the 4-level memory cells may be outweighed by their lack of reliability.